1. Field of the Invention
This invention relates to the field of synchronizing signal separators, and in particular, to the field of adaptive synchronizing signal separators as may be incorporated into an integrated circuit.
2. Description of Related Art
An integrated synchronizing signal separator is utilized in an integrated circuit processor for an auxiliary video signal appearing as the inset picture in a picture-in-picture display, often referred to as a PIP display. The integrated circuit is known as the DPIPIC, and is utilized in television receivers manufactured by Thomson Consumer Electronics, Inc. The integrated synchronizing signal separator in the DPIPIC includes an analog synchronizing signal tip clamp, an analog is to digital converter, a digital low pass filter, a comparator, a horizontal phase locked loop, a nonlinear filter and a digital back porch clamp. The video signal for the auxiliary picture in the PIP display is synchronizing signal tip clamped, digitized and then low pass filtered. A synchronizing signal slicing comparator compares the low pass filtered signal, which represents the luminance component of the auxiliary video signal, to a reference slicing level of about -25 IRE, which is about 15 IRE above the nominal synchronizing signal tip level of -40 IRE. The output of the comparator is a composite synchronizing signal. The horizontal synchronizing signal is separated by a horizontal phase locked loop and the vertical synchronizing signal is separated by the nonlinear filter. The separated horizontal synchronizing signal is an input to a digital back porch clamp, which also receives the luminance component as an input, but which does not otherwise play a part in the synchronizing signal separation. A clamped luminance signal from the digital back porch clamp is used for further video processing in the integrated circuit.
The foregoing approach works well under typical signal conditions, but is more prone to failure when the synchronizing signal is compressed or the signal is noisy. When the synchronizing signal is compressed, errors can result when the video level drops below the slicing threshold. In order to minimize this, the slicing level can be set closer to the synchronizing signal tip level than the -20 IRE level, which is nominally the half way point between synchronizing signal tip and back porch. This degrades noise immunity, but is generally considered the best compromise. The level of performance using a fixed synchronizing signal slicing threshold level is deemed marginally acceptable, as compared to the synchronizing signal processing circuitry for the main video picture, because loss of the synchronizing signal can occur in signals which are weak or have a compressed synchronizing signal, but which are otherwise watchable. In other words, the signal would be watchable as a main picture, but not as an auxiliary picture.
An alternative to a fixed synchronizing signal slicing level is utilized in the ITT digital chip set. The synchronizing signal separator in the ITT digital chip set has two modes of operation. The synchronizing signal slicing level is fixed during synchronizing signal acquisition as in the DPIPIC. After synchronization is established, the synchronizing signal slicing level is set to one half (50%)of the synchronizing signal pulse amplitude by averaging the synchronizing signal tip level and the black level, corresponding to the back porch. This reduces the probability of false triggering due to video levels, because the synchronizing signal slicing level can move closer to back porch as the synchronizing signal tip moves closer to back porch, at least up to a point. Noise immunity is enhanced when the synchronizing signal tip moves away from back porch, because the synchronizing signal slicing level moves away from back porch, at least up to a point. The point at which the improvement from the ITT chip set stops still falls short of a performance level which is substantially comparable to the synchronizing signal separation in the main video channel processing.